
module demux_2output (
    input logic [31:0]     data_in,
    input logic            sel,
    output logic [31:0]    out0,
    output logic [31:0]    out1
);
    assign out0 = (sel == 1'b0) ? data_in : 32'b0;
    assign out1 = (sel == 1'b1) ? data_in : 32'b0;
endmodule